Cost - Effective , High - Performance Giga - Scale Checkpoint / Restore

Computer Engineering Group Technical Report Electrical and Computer Engineering Department University of Toronto November 18, 2004 Abstract This work proposes a novel checkpoint store compression method for giga-scale, coarse-grain checkpoint/restore. This mechanism can be useful for debugging, post-mortem analysis and error-recovery. The effectiveness of our compression method lies in exploiting value locality in the memory data and address streams. Previously proposed dictionary-based hardware compressors exploit the same properties however they are expensive and relatively slow. We observe that because program behavior is typically not very random much simpler mechanisms can offer most of the compression benefits. We propose three compressors that exploit value locality using very small direct mapped structures. Our compressors require few resources, can be easily pipelined and can process one full block per processor cycle. We study two uses of our compressors for post-mortem analysis: (1) Using them alone, and (2) using them in-series with a dictionary-based compressor. When used alone their offer relatively competitive compression rates in most cases. We demonstrate that when combined with previously proposed hardware-based compression methods, our compressors improve overall compression rates while significantly reducing on-chip buffer requirements. Specifically, with an on-chip buffer of just 1K bytes a combination of our compressor with a dictionary-based compressor results into an overall performance slowdown of just 1.6% on the average for storing checkpoints to main memory. Moreover, this combination reduces checkpoints to 34% of their original size. The dictionary-based compressor alone even when used with a 64Kbyte on-chip buffer incurs an overall performance slowdown of 3.7% and reduces checkpoints to 38% of their original size. The worst performance slowdown is 4.4% for our compressor and 11% for the dictionary-based compressor alone. Thus with a lot less resources (1Kbyte vs. 64Kyte on-chip buffering) our technique offers better performance and compression. When used alone, our compressor reduces checkpoint storage to 52% of its original size. While not as good as dictionary-compression this reduction is possible with very few resources (a dictionary-based compressor requires millions of transistors while our compressor few thousand). All aforementioned results are for a checkpoint interval of 256 million instructions.